This invention relates to electronic device fabrication processes and associated apparatus. More specifically, the invention relates to chemical vapor deposition processes for controlling the deposition profile of dielectric layers on semiconductor substrates.
It is often necessary in semiconductor processing to deposit layers of dielectric. For example, blanket layers of dielectric are deposited and patterned to provide electrical isolation between vertical layers of semiconductor or conductor (e.g., metalization) in semiconductor devices (e.g., inter-layer dielectric (ILD) or inter-metal dielectric (IMD), as sacrificial protection layers during semiconductor processing, and to fill trenches to electrically isolate adjacent regions in a semiconductor device (e.g., shallow trench isolation (STI).
In these semiconductor processing techniques, it is often necessary to control the deposition profile of dielectric material on the wafer. Depending on the application, the objective may be control (minimization) of within wafer (wiw) uniformity, deposition of a profile compatible with a subsequent processing technique (e.g., CMP), or high aspect ratio gap fill.
Dielectric deposition processes for semiconductor fabrication applications are well known. For example, TEOS/ozone SACVD (sub atmospheric chemical vapor deposition) has generally provided good results. However, such processes are expiring due to incompatibility with the advanced device constraint of a maximum thermal budget of 700° C.
Going forward, the deposition of silicon dioxide assisted by high density plasma chemical vapor deposition (HDP CVD)—a directional (bottom-up) CVD process—is the method of choice for dielectric deposition, including blanket deposition and high aspect ratio gap-fill.
The deposition profile of HDP CVD deposited dielectrics is essentially dictated by the flow rates of reactant gases (e.g., silane and oxygen), the source power set-point, and the hardware configuration. Therefore, it has often been necessary to modify hardware settings in order to optimize film properties as processes evolve in order to meet requirements of future device generations.
To improve fabrication of advanced technology devices, the art requires better dielectric deposition processes that provide deposition profile control without the need for costly and time consuming hardware modifications.